Multi-way partitioning of VLSI circuits

Partitioning is one of the critical phases of hierarchical design processes like VLSI design. Good partitioning techniques can positively in uence the performance and cost of a VLSI product. This paper proposes a partitioning algorithm with a new cost metric. Viewed from a VLSI layout point of view our cost metric minimizes the average delay per net. It can also be interpreted as achieving the minimum number of vias per net. This paper highlights how the seemingly slight di erence between our metric and others could cause partitions to be evaluated considerably di erently. Experimental results show that in addition to the expected improvements we get on our metric, the proposed algorithm does well on the traditional nets cut metric as well.